Odarushchenko, O. M.Odarushchenko, O. B.Одарущенко, Олег МиколайовичОдарущенко, Олена Борисівна2026-08-032026-08-032020Software Fault Insertion Testing for SIL Certification of Safety PLC-based System / O. Odarushchenko et al. Proceeding of the 11th IEEE International Conference on Dependable Systems, Services and Technologies DESSERT’2020. Pp. 80-84. DOI: 10.1109/DESSERT50317.2020.9125006https://dspace.pdau.edu.ua/handle/123456789/22171The problems of the safety PLC market are analyzed. A tendency of the PLCs transition for industrial applications (for example NPP I&C) in new technologies has been identified. The advantages of FPGA technology for developing safety-based PLCs in comparison with microprocessor technology are formulated. The fault insertion testing (FIT) is considered as one of the mandatory techniques applied in the process of the certification against requirements of IEC 61508 according to safety integrity level (SIL). The concept of the HW FIT-ability is generalized for SW components of FPGA PLC-based safety-critical I&C systems (FPICS) (SW FIT-ability). Procedures, techniques and tools taking into account existing set of insertion variants for SW faults are proposed.enI&C systemsPLC - programmable logic controllerfault insertion testing (FIT)software FITFIT proceduresFIT toolsArticle